As is fundamental in the art, the high performance available from modern integrated circuits derives from the transistor matching that automatically results from the fabrication of all of the circuit transistors on the same integrated circuit chip. This matching results from all of the devices on the same chip being fabricated at the same time with the same process parameters. As such, the circuits operate in a matched manner over wide variations in power supply voltage, process parameters (threshold voltage, channel length, etc.), and temperature.
However, mere matched operation of the devices on the integrated circuit does not guarantee proper operation, but only means that all devices operate in a matched fashion relative to one another. If, for example, the integrated circuit is manufactured at its "high-current corner" conditions (minimum channel lengths, minimum threshold voltages), all transistors in the chip will have relatively high gains, and will switch relatively quickly; the integrated circuit will thus operate at its fastest, especially at low temperature with maximum power supply voltage applied. Conversely, if the integrated circuit is manufactured at its "low-current corner" (maximum channel lengths, maximum threshold voltages), all transistors in the chip will have relatively low gains and slow switching speeds, and the integrated circuit will operate at its slowest rate, especially at high temperature and the minimum power supply voltage. Accordingly, the factors of processing variations, power supply voltage, and temperature greatly influence the speed and overall functionality of the integrated circuit.
The circuit designer must take these variations into account when designing the integrated circuit. For example, the circuit designer may wish to have a certain internal clock pulse to occur very quickly in the critical data path of an integrated memory circuit. However, the above-noted variations in process, voltage and temperature limit the designer's ability to set the fastest timing of the clock pulse at the slowest conditions (low-current process corner, low voltage, high temperature) without considering that the circuit may be so fast at its fastest conditions (high-current process corner, high voltage, low temperature) that the clock may occur too early or the clock pulse may be too narrow. An example of such an internal clock pulse is the clock pulse for the sense amplifier in an integrated circuit memory for which delay directly affect access time; if the sense amp clock occurs too early, however, incorrect data may be sensed.
As is well known in the art, a typical method for controlling the switching time of a circuit is to insert one or more series transistors in the switching path, and control the current through the series transistor with a bias voltage. Control of the bias voltage, in a manner that is compensated for the desired parameter, can thus control the switching of the circuit in a compensated manner.
Referring now to FIG. 1, the use of a series transistor to control the switching of an output stages of a conventional integrated circuit, such as microprocessors, memories and the like, will now be described.
The circuitry of FIG. 1 presents digital logic states on output terminals OUT.sub.i, OUT.sub.j responsive to digital signals produced on lines DATA.sub.i, DATA.sub.j by functional circuitry, not shown, that is resident on the same integrated circuit chip. Output terminals OUT.sub.i, OUT.sub.j as illustrated in FIG. 1 are suggestive of bond pads at the surface of an integrated circuit chip, and as such are directly connected by way of wire bonds, beam leads, and the like to external terminals of a packaged integrated circuit. As such, certain other circuitry, such as electrostatic discharge protection devices and the like, while not shown, will typically be implemented along with the circuitry of FIG. 1. In addition, while the circuitry of FIG. 1 is illustrated for driving dedicated output terminals OUT.sub.i, OUT.sub.j, the output drive circuitry may drive common input/output terminals that not only present data but also receive data from external to the integrated circuit.
In the example of FIG. 1, output driver 2.sub.i drives output terminal OUT.sub.i with a logic state corresponding to the logic state present on line DATA.sub.i, while output driver 2.sub.j drives output terminal OUT.sub.j with a logic state corresponding to the logic state present on line DATA.sub.j. It is of course contemplated that more than two output drivers 2 are likely to be present on the integrated circuit chip; for example, modern microprocessor and memory devices may have up to as many as sixteen or thirty-two output terminals, and thus as many as sixteen or thirty-two output drivers 2. Output drivers 2.sub.i, 2.sub.j are similarly constructed, and as such the following description of output driver 2.sub.i is contemplated to also describe the construction and operation of other output drivers 2 on the same integrated circuit.
Output driver 2.sub.i is of the CMOS push-pull type, and as such includes p-channel pull-up transistor 4 and n-channel pull-down transistor 8. The drains of transistors 4 and 8 are connected together to output terminal OUT.sub.i, with the source of transistor 4 biased to V.sub.cc and the source of transistor 8 biased to ground. Input data line DATA.sub.i is connected, via inverting buffer 6, to the gate of p-channel pull-up transistor 4. Input data line DATA.sub.i is coupled to the gate of n-channel pull-down transistor 8 by way of an inverting logic function made up of transistors 10, 12, 14, such logic function also serving to control the switching, or slew, rate of output driver 2.sub.i as will become evident from the description hereinbelow.
The gate of n-channel pull-down transistor 8 is driven from the drains of p-channel transistor 12 and n-channel transistor 14, the gates of which are connected to input data line DATA.sub.i. As such, transistors 12, 14 implement a logical inversion of the logic state of input data line DATA.sub.i. The source of transistor 14 is biased to ground, while the source of transistor 12 is connected to the drain of p-channel bias transistor 10, which has its source biased to V.sub.cc. The gate of p-channel bias transistor 10 is driven by a bias signal (on line BIAS) generated by bias circuit 5. In this arrangement, the current conducted by transistor 10 controls the drive current of transistor 12 when input data line DATA.sub.i is low (i.e., when transistor 8 is to be turned on), and thus the rate at which the gate of transistor 8 is pulled high responsive to a transition of input data line DATA.sub.i from high-to-low. The current of transistor 10 thus controls the rate at which pull-down transistor 8 is turned on when output terminal OUT.sub.i is to be switched from a high logic level to a low logic level.
As is well known in the art, inductive noise is generated as a result of the time rate of change of current applied to a load (dV=L di/dt). Higher switching speed thus generally results in increased noise, since the time rate of change of the current increases. Circuit designers generally select an operating point at an optimized condition, relative to switching speed and noise. In order to maintain this optimized operation, bias circuit 5 presents a bias voltage on line BIAS that is compensated for variations in power supply voltage, temperature, and process variations.
In the CMOS arrangement of FIG. 1, n-channel pull-down transistor 8 switches at a much faster rate than does p-channel pull-up transistor 4; this is due to the typically higher channel mobility for n-channel transistors than for p-channel transistors, as is well known in the art. As such, in the example of FIG. 1, slew rate control is only used to control the rate at which n-channel pull-down transistor 8 is turned on, and not the rate at which p-channel pull-up transistor 4 is turned on.
Prior techniques for generating the bias voltage on line BIAS via bias circuit 5 have been limited, however. One common technique is to use a bias circuit 5 that attempts to compensate for temperature variations. As is known in the art, the threshold voltage of a MOS transistor varies inversely with temperature. Accordingly, prior techniques have compensated for variations in temperature by relying on threshold voltage variations to produce a compensating bias voltage. For example, in the circuit of FIG. 1, bias circuit 5 may adjust the voltage on line BIAS to follow variations of a p-channel transistor threshold voltage, so that the quantity .vertline.V.sub.gs -V.sub.tp.vertline. for transistor 10 would remain constant over temperature.
It has been found, however, that use of threshold voltage based bias circuits are not well-suited to compensate for both temperature variations and process parameter variations, however, since the threshold voltage is itself a process parameter. Variations in the process parameters may thus affect the ability of the circuit to compensate for temperature. Indeed, it has been observed that conventional bias voltage generating circuits that are compensated for temperature are not well compensated for variations in power supply voltage and process variations.
It is therefore an object of the present invention to provide a bias circuit for producing a compensated bias voltage that follows variations in power supply voltage and process parameters.
It is a further object of the present invention to provide such a bias circuit that robustly compensates for variations in power supply voltage and process parameters, such that temperature variations need not be considered.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.